State-of-the-art semiconductor circuits are complicated devices which are constructed using exceedingly complex, multi-step processes including handling, photolithographic printing, and chemical processing. The photolithographic printing and chemical processing steps permit the creation of many types of structures required by semiconductor circuits, including diffusion areas for active devices (transistors), polysilicon for transistor gates and interconnect, and various types of metal—including copper—for interconnect. The number of handling, printing, and processing steps may easily run to the thousands. Design feature sizes of the components making up the circuits are routinely smaller than the wavelength of visible light. The number of active devices in a circuit (transistors) may easily run to the tens or hundreds of millions. In addition, rapidly changing market demands and needs drive manufactures to produce circuits with ever-increasing device counts and performance, chip feature sets, system flexibility and versatility, and a variety of other system demands. Often, these disparate demands are mutually exclusive, forcing manufacturers to choose one feature at the expense of others. In addition, the high cost of manufacturing circuits means designers must verify their circuit designs before chips are actually built. To ensure that the chips being built are indeed correct, the design verification process must be extensive and meticulous. After a circuit design is tested, the results are compared to a design specification to ensure that the design can meet the many, and at times, divergent requirements imposed on the design. Ensuring that a design matches its specification becomes more complex with increased circuit operating frequency; as circuit operating frequency increases, wires look like transmission lines and circuit performance changes due to frequency dependent effects. In addition to frequency dependencies, traditional requirements (such as timing, power, and heat, to name only a few) must also be considered. The designer must show, using careful testing protocols, that the circuit meets each of the design requirements, or else the circuit will not function as designed.
Designers have known for years that testing a circuit design must take into account the many physical characteristics of the circuit being tested—the device under test (DUT). These physical characteristics include the sizes of the devices, operating temperature, the parasitic circuit elements associated with the interconnect (i.e. wires), and the pattern and proximity of the interconnect, to name a few. The parasitic circuit elements include resistance (R) and capacitance (C), whether the interconnect material is diffusion, polysilicon, or metal. These Rs and Cs, as they are known, significantly impact the ability of a circuit to perform its intended task. The parasitic Rs and Cs limit the maximum and minimum speeds of a circuit, as well as affecting the ability of a circuit to perform its intended function at all. For circuits operating at sufficiently high clock rates, the metal interconnect of the chip can become an even more significant design problem because of the introduction of a third parasitic element type, inductance (L). The introduction of inductance (L) complicates effort to model a design's interconnect since the designer must take into account three parasitic effects. The long lines of semiconductor chips and printed circuit boards can begin to look less like a conventional wire and more like a transmission line in high frequency design. When the frequency gets higher still, losses must be introduced into the transmission-line model due to yet an additional factor, conductance (G). It is imperative that circuit testing accurately and efficiently model interconnect in a cost-effective manner.